Author : Dass, P.
European Journal of Molecular & Clinical Medicine,
2020, Volume 7, Issue 4, Pages 2726-2735
A low-power comparator is presented. PMOS transistors are used at the input of the pre amplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough pre-amplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the pre amplifier gain and decrease the input common mode of the latch to strongly turn on the PMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for pre-amplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified