Keywords : RALU
European Journal of Molecular & Clinical Medicine,
2020, Volume 7, Issue 4, Pages 2376-2382
In this document a simple 32 bit RISC based MIPS type processor by using Peres Reversible Logic Gates, which gives transaction in delay and frequency. The synthesis and simulation is conceded out by using XILINX ISE 14.5 and HDL is urbanized by means of VHDL language with vertex device. The smart world looking in making of smart gadgets by using processors and decade by decade the speed and other parameters are getting minimized for better performance. here introducing to RISC based MIPS architecture based processor for high speed is done .which works without compiler where the existed general processor is in use of .with the use of MIPS RISC architecture the arithmetical, logical and shift functions are done in reduced time as there is reduced instruction set computer, it employs a good number of registers than to transistors. The processor internally consists of some blocks so that the operations are performed. RALU(reversible gate arithmetic logic unit) is considered to be the main module of the processor which provides task functions and other blocks are also exists such as control unit ,program counter ,instruction register ,memory .