Online ISSN: 2515-8260

Keywords : ADC


LOW-POWER AND HIGH-SPEED CMOS COMPARATOR FOR ADC APPLICATION

P. Dass; Dr.J. Mohana

European Journal of Molecular & Clinical Medicine, 2020, Volume 7, Issue 4, Pages 2726-2735

A low-power comparator is presented. PMOS transistors are used at the input of the pre amplifier of the comparator as well as the latch stage. Both stages are controlled by a special local clock generator. At the evaluation phase, the latch is activated with a delay to achieve enough pre-amplification gain and avoid excess power consumption. Meanwhile, small cross-coupled transistors increase the pre amplifier gain and decrease the input common mode of the latch to strongly turn on the PMOS transistors (at the latch input) and reduce the delay. Unlike the conventional comparator, the proposed structure let us set the optimum delay for pre-amplification and avoid excess power consumption. The speed and the power benefits of the comparator were verified

A LOW POWER OPERATIONAL AMPLIFIER DESIGN USING 18NM FIN-FET TECHNOLOGY FOR BIOMEDICAL APPLICATIONS

Hari Kishore Kakarla; Mukil Alagirisamy

European Journal of Molecular & Clinical Medicine, 2020, Volume 7, Issue 1, Pages 2322-2334

Bioelectric impedances have been found to correlate with a number of biological phenomena in some tissues, organs, and cells. This has helped to advance several of today's bioelectric impedance applications, like Electrical Impedance Tomography (EIT), Electrical impedance spectroscopy (EIS). For calculating bioelectric impedance it is very important to design low power Analog Front end consisting of Op-amp and ADC. In this paper, a low supply voltage based FinFET operational amplifier and its characteristics are studied and designed by using Cadence 18nm FinFET technology. The standard characteristics of the op-amp like gain, bandwidth, unity gain bandwidth product, settling time and so on are distinguished with the existing architectures. The suggested FinFET-based amplifiers are having a greater performance at a reduced voltage than conventional two-stage Op-amps. In this work, supply voltage is provided as 0.8V. The circuit consumes a power of 35 μW, provides a gain of 83 dB and unity gain repeat of 10 MHz with a phase edge of 70 degrees. The difference between the suggested architecture and standard two stage CMOS Op-amp shows that figure of Merit for proposed circuit is improved to 1.1pj.