European Journal of Molecular & Clinical Medicine2515-82607920220625DESIGN OF 4-BIT MULTIPLIER ACCUMULATOR UNIT BY USING REVERSIBLE LOGIC GATES IN PERES LOGIC241524226828ENDr.K. GunasekaranSiddartha Institute of Science and TechnologyChanda LaxmanaSudheerSiddartha Institute of Science and TechnologyV. SornagopalG R T Institute of Engineering and TechnologyDr.M. GnanasekaranSri Venkateshvara Polytechnic College, Vellore, T. N, INDIAJournal Article20210118—In VLSI circuits Heat is a major problem. However, in reversible logic, the measurement of heat dissipation is zero. In this sense, it is an important work in nanotechnology, low energy complementary metal oxide semiconductor structures [CMOS]. For reversible logic, no results are lost. However, this limits the delay in the scope of the hardware equipment. Therefore, reversible logic technology can be used to reduce energy distribution, reduce heat wave propagation and increase speed. Therefore, it is used to increase speed and reduce energy consumption. In this paper we are going to represent the following reversible logic gates, such as Fredkin gates, Peres, Feynman, Toffoli. This paper proposes a reversible logic design of a 4-bit MAC structure using Peres gates as reversible logic blocks. In addition, a variety of parameters, along with those of conventional computing, perform a relative test between classical style and quantum logic operation. The proposed approach is implemented using Xilinx-7 FPGA in VHDL.https://ejmcm.com/article_6828_d2df2c7ffded0d339696e731387c3441.pdf