VLSI Design of High Speed and Area Efficient Radix-8 Serial Parallel Multiplier
European Journal of Molecular & Clinical Medicine,
2020, Volume 7, Issue 4, Pages 2265-2271
AbstractMultiplier is one of the hardware components that typically consumes a significant chip region which requires to be reduced and can be helpful to a wide range of applications whereby multiplication components are an essential device, such as digital signal processing (DSP) systems or computational methods. The proposed method it accelerates applicants like digital filter, machine learning and neural networks by developing a two-speed radix-8 serial parallel multiplier. Proposed multiplier is a variation of the adapted radix-8 Booth multiplier serial – parallel (SP), which only incorporates nonzero Booth encoding along with skips over zero functions, allowing latency based on the multiplier size. This study focused on DSP applications where in multiplier remains being used substantially and suggests strategy that helps to minimize the hardware as well as latency contributing to improved device output and thereby helps to improve the running frequency by a substantial amount. An 8-bit multiplier was designed using a booth multiplication of radix-4, which decreases number of partial products.
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