DESIGN AND PERFORMNCE ANALYSIS OF LOW DENSITY PARITY CHECK ENCODER AND DECODER
European Journal of Molecular & Clinical Medicine,
2020, Volume 7, Issue 9, Pages 2223-2230
AbstractHere it proposes new low-density parity-check (LDPC) encoder architecture and a parallel low-density parity-check (LDPC) decoding algorithm on GPUs. In this paper the basic construction of effective LDPC parity matrix is transformed in to parallel encoding operations of rows and columns. An optimized method for controlling memories is also proposed which can be reused with different code rates which enhance the use of components assets. Then the planned LDPC encoder along with decoders is designed with Xilinx FPGA software. Confer into Modelsim's results, it can again authenticated that the proposed technique is advantageous by less assets usage, less required power and also precision is high. Then proposed encoders and decoders brings in a throughput of 400 Mbps. Among the test data transmission with Lena base binary images this paper presents a effective design and implementation for LDPC decoder, dedicated application specific integrated circuit (ASIC) or field-programmable gate array (FPGA) constructions into later years to support huge performance given their lengthy deployment period, huge level construction along with particularly rigid functionality. Any other way, effective software system constructions on GPU provide versatile, expandable, and low cost solution in shorter deployment periods. This can acquire high throughput in computerized correspondence frameworks, it presents minimum GPU-based advancements about major LDPC decoder algorithms.
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