Design of 24 Bit Vedic Multiplier Using GDI Technique in 32 Bit Floating Point Multiplier
European Journal of Molecular & Clinical Medicine,
2020, Volume 7, Issue 11, Pages 2725-2737
Abstract
Multiplier is the common hardware block present in any processor. Floating point multiplier’s can be found in electronic systems that run complex calculations especially in DSP processor. The Floating point numbers are commonly used in numerous applications because of their effective capability in representation of numbers. The feasible way of presenting real numbers in binary format is done by using FP numbers. A 24 bit Vedic multiplier using GDI technique is designed in this paper. Multiplication of two numbers will take more time and many steps. For the unsigned mantissa multiplication in the FP multiplier the Vedic mathematics sutra called UT is used. Any logic circuit can be designed by using CMOS logic. The CMOS logic will consumes more area. The numbers of transistors in the circuit are reduced by using GDI logic. Thus the Vedic mathematics will reduce the delay and the GDI logic will reduce the transistors count in a circuit which in turn reduces the power.
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