The reverse propagate adder (RCPA) is presented in this project. In this project. Under the RCPA framework, the transmission signal stretches from the most important to the less significant bit in a counter-flow way; thus the transportation signal is more appropriate than the production. In the case of delay differences, this propagation process improves stability. The cell with a varying pause, capacity, energy and accuracy are implemented in three separate implementations of the reverse transportation (RCPFA). The configuration suggested can be linked along with the precise (forward) adder to shape the hybrid adders with precise tuning levels. In contrast to modern estimated additions, the specification parameters of the proposed RCPA architectures and several hybrids that have been implemented using these frameworks are discussed. Using Reverse Carrier Adder (RCPA), the Fir Filter is applied. Project with Verilog will be created. For simulation and synthesis, the Xilinx ISE tool is used