One of the most and commonly adopted video compression standards today is the advanced H.265/HEVC, commonly used for many applications due to high speed, optimized area and good throughput. Examples of such major applications are communications, networking, image processing digital signal processing and real time video applications. The current design having the use of the modified inverse discrete cosine transforms to perform video decompression. A new detailed implementation described to analyze the behavior of the encoding and also the transform takes residual data and transforms it from the spatial domain to the frequency domain. This frequency domain representation can then be compressed, using quantization, while still retaining a high level of video quality when decoded and presented to the user. The encoder and decoder implementation done in Verilog and synthesized using sophisticated cadence tool Genus. A hardware implementation of the inverse quantization and inverse transform, compliant to the HEVC standard, will be developed. The current design high targets the 4x4 inverse quantization, transform, synthesis and place & route using the Nan gate 45 nm technologies Open Cell Library. A digital implementation using Innovus tool was used for the design with development and also done analysis of speed, area and throughput will be carried out for the current applications and compared to similar ASIC designs. The required operational frequency of this design will support 4K video at up to 40 frames/sec. The main core area of this digital design takes up 10224 µm2 and can operate at maximum frequency of 400 MHz.