Approximate computer arithmetic circuits based on CMOS technology have been extensively studied. Designs of approximate adders, multipliers and dividers for both fixed point and floating-point formats have been proposed. As a new paradigm in the nano scale technologies, approximate computing enables error tolerance in the computational process, it has also emerged as a low power design methodology for arithmetic circuits. Majority logic (ML) is applicable to many emerging technologies and its basic building block (the 3-input majority voter) has been extensively used in digital circuit design. In this project, we propose the design of a one bit approximate full adder based on majority logic. Furthermore, multi-bit approximate full adders are also proposed and studied, the application of these designs to quantum-dot cellular automata (QCA) is also presented as an example. The designs are evaluated using hardware metrics (including delay and area) as well as error metrics. Compared with other circuits found in the technical literature, the optimal designs are found to offer superior performance. Approximate half adder and full adder is designed. These Half adder and Full adder combinations are used to implement the Brent Kung Adder and multiplier. In the present work fast adders like RCA adders using compressor methodology and multiplication operations are performed by utilizing Majority gates. This paper also proposes the Wallace tree multiplier using proposed majority based Full adder .The designed multiplier is effective and efficient in terms of area-delay trade off, delay(speed) and power utilization.Project will be developed using verilog HDL. Xilinx ISE tool is used to perform the Simulation and Synthesis.