A Novel High Speed Parallel structure to Shapiro technique is proposed to XCV 600e-8fg676 target device. The main component in the parallel structure is binary comparator which offers less time delay. The Parallel structure of Shapiro technique is differentiated with 1D sorting and elevated in faster operation. The Proposed architecture was also compared with 9 element sorter that required 25 comparators of same class. It was found that the proposed architecture is faster to its counterparts. Hence High Speed VLSI architecture is proposed for arranging 9 elements in increasing order.